1. Field of the Invention
The invention relates to a display panel drive device that drives a display panel such as a plasma display panel, and in particular relates to a display panel drive device arranged to drive a scanning electrode by changing over the output level of the drive signal output terminal among three levels, namely, a low side level output, high side level output and a high impedance level output.
2. Description of the Related Art
In recent years, large-screen thin, wall-hanging television sets using a plasma display panel (hereinbelow abbreviated as PDP) have attracted considerable attention.
FIG. 9 is a block diagram showing the construction of a PDP drive device.
In this case, for simplicity, the example of a PDP comprising two electrodes, namely, a scan/sustain electrode and a data electrode, will be described.
The drive device of a PDP 100 comprises, for example a plurality of scan driver ICs (integrated circuits) 200-1, 200-2, 200-3, . . . , 200-k, and data (address) driver ICs 300-1, 300-2, 300-3, . . . , 300-m (where k and m are arbitrary integers).
The scan driver ICs 200-1 to 200-k drive a respective plurality of scan/sustain electrodes 111 and the data (address) driver ICs 300-1 to 300-m drive a plurality of data electrodes 112 corresponding to the respective colors red (R), green (G) and blue (B). These scan/sustain electrodes 111 and data electrodes 112 are arranged in the form of a grid so as to be mutually perpendicular; discharge cells (not shown) are arranged at the intersections of this grid.
Regarding the number of scan driver ICs 200-1 to 200-k, assuming for example that 64 scan/sustain electrodes 111 can be driven respectively thereby, in the case of an XGA (extended video graphics array), since the number of pixels of the PDP 100 is 1024×768, k (=12) scan driver ICs must be provided.
In the case of display of an image by means of these scan driver ICs 200-1 to 200-k and data (address) driver ICs 300-1 to 300-m, data from the data electrodes 112 is scanned and written to each scan/sustain electrode 111 in the discharge cells (during an address discharge period). Discharge is maintained by outputting, a number of times, discharge sustaining pulses to the scan/sustain electrodes 111 (discharge sustaining period), thereby effecting image display.
The construction of such a scan driver IC is described below. Hereinbelow a scan driver IC will be termed a “display device drive circuit.”
FIG. 10 is a view showing the construction of a conventional display device drive circuit. A conventional display device drive circuit 200 includes shift registers 210-1, 210-2, 210-3, . . . , 210-n that receive serial data signal DATA. The serial data signal DATA control the scan/sustain electrodes 111 shown in FIG. 9. The shift registers 210-1, 210-2, 210-3, . . . , 210-n convert the received DATA into parallel signals in synchronization with the clock signal CLK. Data selectors 220-1, 220-2, 220-3, . . . , 220-n deliver to output circuits 230-1, 230-2, 230-3, . . . , 230-n signals transferred for each bit from the shift registers 210-1, 210-2, 210-3, . . . , 210-n. The number n is arbitrary: for example in the case of a 64-bit display device drive circuit 200, n=64 and the display device drive circuit 200 drives 64 scan/sustain electrodes 111. The data selectors 220-1, 220-2, 220-3, . . . , 220-n are connected with a low side power source VDL and input a voltage corresponding to the total output H-level fixed signal when all of the scan/sustain electrodes 111 are set at the H (High) level. Also, the grounded terminals GNDH input a total output L level fixed signal when all of the scan/sustain electrodes 111 are set at the L (Low) level.
FIG. 11 is a view showing an output stage circuit employed in a conventional display device drive circuit.
The output circuit 230 includes a selector circuit 235 comprising a level shifter circuit 231, inverters 232 and 233, an inverter (serving as a buffer circuit) 234, and elements that pass a large current per unit area such as for example two n-channel IGBTs (insulated gate bipolar transistors) 236, 237.
The level shifter circuit 231 is a circuit comprising high withstand-voltage p-channel MOSFETs (metal oxide semiconductor field effect transistors) (hereinbelow referred to as Pch-MOS) 231a, 231b and n-channel MOSFETs (hereinbelow called Nch-MOS) 231c, 231d. 
The Pch-MOS 231a has its source terminal connected with a high-voltage power source terminal that supplies high voltage (high side power source VDH) of 0 to 100 V and has its drain terminal connected with the drain terminal of the Nch-MOS 231c, the gate terminal of the Pch-MOS 231b and the gate terminal of the IGBT 236. The gate terminal of the Pch-MOS 231a is connected with the drain terminal of the Pch-MOS 231b and the drain terminal of the Nch-MOS 231d. Also, the Pch-MOS 231b likewise has its source terminal connected with the high side power source VDH and its drain terminal connected with the drain terminal of the Nch-MOS 231d and the gate terminal of the Pch-MOS 231a. The gate terminal of the Pch-MOS 231b is connected with the drain terminal of the Pch-MOS 231a. The source terminals of the Nch-MOSs 231c and 231d are grounded. Also, the low side power source VDL (signal IN delivered from the aforementioned data selectors 220-1 to 220-n) from the input terminal 241 is input through the inverter 232 to the gate terminal of the Nch-MOS 231c and is input through the inverters 232, 233 to the gate terminal of the Nch-MOS 231d. 
The low side power source VDL from the input terminal 241 is input to the buffer circuit 234 through the inverters 232, 233 and is input to the gate terminal of the IGBT 237 after inversion of the signal level thereof.
The collector terminal of the IGBT 236 is connected with the high side power source VDH and the emitter thereof is connected with the output terminal 243 (Do) and the collector of the IGBT 237. Also, the emitter of the IGBT 237 is grounded.
The output terminal 243 is connected with the scanner/sustain terminal 111 as shown in FIG. 9 and is additionally connected with a discharge cell (regarded as a capacitance) A logic signal of 0 to 5 V from the low side power source VDL is sent to the selector circuit 235 and is directly output to the gate terminal of the IGBT 237 that controls the low side output. Also, it is converted to a logic signal of 0 to 100 V by the level shifter circuit 231 and supplied to the gate terminal of the IGBT 236 that controls the high side output. Although, in the case of these output circuits 230, for both the high side (power source side) and the low side (ground side), totem pole type output circuits are constituted as shown in FIG. 10 by the n-channel IGBTs 236, 237, a similar circuit construction also could be achieved using MOSFETS.
Also, a Zener diode 244 and resistance 245 are connected between the gate and emitter of the IGBT 236 connected with the high side power source VDH. The Zener diode 244 prevents application of voltage exceeding the withstand voltage between the gate and emitter of the IGBT 236; the resistance 245 pulls the gate potential up to the low side power source VDL (5 V). Since high voltage cannot be applied between the gate and emitter of the IGBT 236 due to the connection of the Zener diode 244, the gate oxide film of the IGBT 236 can be formed comparatively thin and may be for example of the same thickness as the low side IGBT 237. If the gate oxide film of the IGBT 236 is thick, the Pch-MOS 231a and Pch-MOS 231b constitute high withstand-voltage elements, so the gate oxide film likewise must be thick. If the gate oxide film of the IGBT 236 and the gate oxide film of the Pch-MOS 231a and Pch-MOS 231b are respectively formed of the same thickness in order to reduce the number of process steps, it is necessary to make the Pch-MOS 231a and Pch-MOS 231b large. However, if a Zener diode 244 is formed, the Pch-MOS 231a and Pch-MOS 231b can be formed without increasing the number of process steps and without making the area occupied by the circuit large. Such a construction of the output stage circuit is disclosed for example in Laid-open Japanese Patent Application No. 2000-164730 (FIG. 1).
It should be noted that the details of for example the wiring pattern and mounting onto the board in the conventional display device drive circuit 200, are disclosed, for example, in Laid-open Japanese Patent publication No. 2002-341785. Also, in Laid-open Japanese Patent publication No. H. 11-98000 (paragraph numbers [0019] to [0023], and FIGS. 1 and 2), in order to prevent generation of noise if the rise of the output signal is too fast, a technique is disclosed of moderating the rise of the output (supplied current) by clamping the gate/source voltage of the FET connected between the output terminal and the high-voltage power source terminal of the output stage to a fixed potential for a fixed portion of the switching time. Also, Laid-open Japanese Patent Application No. 2001-134230 (FIG. 1) discloses a technique for obtaining a sufficient current drive capability even if the transistor connected between the output terminal and the reference power source terminal is made small in order to reduce the chip size.